Optimizing Fault Coverage for Error Resilient Applications: An Integer Linear Programming Formulation

In recent years, a number of high level applications have been reported to be tolerant to errors resulting from a sizeable fraction of all single stuck-at faults in hardware. Production testing of devices targeted towards such applications calls for a test vector set that is tailored to maximize the coverage of faults that lead to functionally malignant errors while minimizing the coverage of faults that produce functionally benign errors. Given a partitioning of the fault set as benign and malignant, and a complete test vector set that covers all faults, we formulate an integer linear programming (ILP) problem to find an optimal test vector set that maximizes coverage of malignant faults and minimizes coverage of benign faults. The proposed formulation guarantees the global optimum solution–zero coverage of benign faults and 100% coverage of malignant faults–if it exists. Further, for cases where a global optimal solution does not exist, solutions with better coverage of malignant faults can be obtained by augmenting the initial test vector set with additional vectors. As a case study, we demonstrate the proposed ILP based test optimization on three adder circuits: 16-bit ripple carry adder, 16-bit lookahead carry adder, and 16-bit carry select adder. We find that the proposed ILP based optimization gives a reduction of about 90% in fault coverage of benign faults while ensuring 100% coverage of malignant faults. This typically translates to an (early manufacturing) yield improvement of over 20% over what would have been the yield if both malignant and acceptable faults are targeted without distinction by the test vector set.